M 级XQ17V16CC44M/ N级 XQ17V16VQ44N 优势渠道
QPro XQ17V16 Military 16 Mb QML Configuration PROM
一般情况下原厂不会备现货，所以普遍情况下货期 大约在 16-20周 。有可能以后在途订单 。此型号生命周期长 非常适合用于新产品设计但是单价较贵 。工程师如有技术问题可以咨询黄小姐：
实物照片
Features
特征
• 16Mbit storage capacity
•16mbit存储容量
• Guaranteed operation over full military temperature
保证操作超过完全军事温度
range: –55°C to +125°C
范围：- 55°C至125°C
• One-time programmable (OTP) read-only memory
•一次性可编程（OTP）只读存储器
designed to store configuration bitstreams of Xilinx
用来储存Xilinx配置比特流
FPGA devices
FPGA设备
• Dual configuration modes
二元配置模式
- Serial slow/fast configuration (up to 20 Mb/s)
-串行慢速/快速配置（高达20兆/秒）
- Parallel (up to 160 Mb/s at 20 MHz)
-并行（高达160兆/秒在20兆赫）
• Simple interface to Xilinx QPro FPGAs
简单的界面qpro•Xilinx FPGA
• Cascadable for storing longer or multiple bitstreams
•级联存放较长或多个比特流
• Programmable reset polarity (active High or active
可编程复位极性（高电平或有源电平
Low) for compatibility with different FPGA solutions
Low）与不同的FPGA解决方案的兼容性
• Low-power CMOS Floating Gate process
•低功耗CMOS浮栅工艺
• 3.3V supply voltage
•3.3V电源电压
• Available in compact plastic VQ44 and ceramic CC44
•可在紧凑的塑料和陶瓷vq44 cc44
packages
包装
• Programming support by leading programmer
编程支持由领先的程序员
manufacturers.
制造商.
• Design support using the Xilinx Alliance and
•设计支持使用赛灵思联盟
Foundation series software packages.
基础系列软件包。
• Guaranteed 20 year life data retention
保证20年的生命数据保持
Description Xilinx introduces the high-density QPro™ XQ17V16 series QML configuration PROM which provide an easy-to-use, cost-effective method for storing large Xilinx FPGA configuration bitstreams. The XQ17V16 is a 3.3V device with a storage capacity of 16 Mb and can operate in either a serial or byte wide mode. See Figure 1 for a simplified block diagram of the XQ17V16 device architecture. When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising clock edge, data appears on the PROM DATA output pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. Once configured, it disables the PROM. When the FPGA is in Slave Serial mode, the PROM and the FPGA must both be clocked by an incoming signal. When the FPGA is in Master SelectMAP mode, it generates a configuration clock that drives the PROM and the FPGA. After the rising CCLK edge, data are available on the PROMs DATA (D0-D7) pins. The data will be clocked into the FPGA on the following rising edge of the CCLK. When the FPGA is in Slave SelectMAP mode, the PROM and the FPGA must both be clocked by an incoming signal. A free-running oscillator may be used to drive CCLK. See Figure 2. Multiple devices can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family. For device programming, either the Xilinx Alliance or Foundation series development system compiles the FPGA design file into a standard Hex format, which is then transferred to most commercial PROM programmers.
