ADC08D500
The ADC08D500 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 500 MSPS. Consuming a typical 1.4 Watts at 500 MSPS from a single 1.9 Volt supply, this device is ensured to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.5 ENOB with a 250 MHz input signal and a 500
该ADC08D500是双，低功耗，高性能CMOS模数转换器，数字化的信号为8位分辨率，采样速率高达500 MSPS。在500 MSPS的从一个1.9伏的电源消耗的一个典型的1.4瓦，这个装置是保证无失码在整个工作温度范围。独特的折叠内插结构，全差分比较器的设计，创新设计的内部采样保持放大器和自校准方案使一个非常平坦的响应各种动态参数超越Nyquist，带有一个250 MHz的输入信号和500生产高7.5位数
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特性
Internal Sample-and-Hold
Single +1.9V ±0.1V Operation
Choice of SDR or DDR Output Clocking
Interleave Mode for 2x Sampling Rate
Multiple ADC Synchronization Capability
特性
内部采样和保持
单1.9±0.1v操作
特别提款权或DDR输出时钟选择
交错倍采样率模式
多个ADC同步能力
深圳市国宇航芯科技有限公司
项目销售工程师 黄云艳
电话
手机
QQ
The ADC08D500 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 500 MSPS. Consuming a typical 1.4 Watts at 500 MSPS from a single 1.9 Volt supply, this device is ensured to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.5 ENOB with a 250 MHz input signal and a 500
该ADC08D500是双，低功耗，高性能CMOS模数转换器，数字化的信号为8位分辨率，采样速率高达500 MSPS。在500 MSPS的从一个1.9伏的电源消耗的一个典型的1.4瓦，这个装置是保证无失码在整个工作温度范围。独特的折叠内插结构，全差分比较器的设计，创新设计的内部采样保持放大器和自校准方案使一个非常平坦的响应各种动态参数超越Nyquist，带有一个250 MHz的输入信号和500生产高7.5位数
特性
Internal Sample-and-Hold
Single +1.9V ±0.1V Operation
Choice of SDR or DDR Output Clocking
Interleave Mode for 2x Sampling Rate
Multiple ADC Synchronization Capability
特性
内部采样和保持
单1.9±0.1v操作
特别提款权或DDR输出时钟选择
交错倍采样率模式
多个ADC同步能力
深圳市国宇航芯科技有限公司
项目销售工程师 黄云艳
电话
手机
